480 lines
15 KiB
C
480 lines
15 KiB
C
#include "ov7670.h"
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#include "pinning.h"
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#include "debug.h"
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#define REG_GAIN 0x00
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#define REG_BLUE 0x01
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#define REG_RED 0x02
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#define REG_VREF 0x03
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#define REG_COM1 0x04
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#define REG_BAVE 0x05
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#define REG_GbAVE 0x06
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#define REG_AECHH 0x07
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#define REG_RAVE 0x08
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#define REV_COM2 0x09
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#define REG_PID 0x0a
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#define REG_VER 0x0b
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#define REG_COM3 0x0c
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#define REG_COM4 0x0d
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#define REG_COM5 0x0e
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#define REG_COM6 0x0f
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#define REG_AECH 0x10
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#define REG_CLKRC 0x11
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#define REG_COM7 0x12
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#define REG_COM8 0x13
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#define REG_COM9 0x14
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#define REG_COM10 0x15
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#define REG_HSTART 0x17
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#define REG_HSTOP 0x18
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#define REG_VSTRT 0x19
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#define REG_VSTOP 0x1a
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#define REG_PSHIFT 0x1b
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#define REG_MIDH 0x1c
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#define REG_MIDL 0x1d
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#define REG_MVFP 0x1e
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#define REG_LAEC 0x1f
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#define REG_ADCCTR0 0x20
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#define REG_ADCCTR1 0x21
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#define REG_ADCCTR2 0x22
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#define REG_ADCCTR3 0x23
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#define REG_AEW 0x24
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#define REG_AEB 0x25
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#define REG_VPT 0x26
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#define REG_BBIAS 0x27
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#define REG_GbBIAS 0x28
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#define REG_EXHCH 0x2a
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#define REG_EXHCL 0x2b
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#define REG_RBIAS 0x2c
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#define REG_ADVFL 0x2d
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#define REG_ADVFH 0x2e
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#define REG_YAVE 0x2f
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#define REG_HSYST 0x30
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#define REG_HSYEN 0x31
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#define REG_HREF 0x32
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#define REG_CHLF 0x33
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#define REG_ARBLM 0x34
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#define REG_ADC 0x37
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#define REG_ACOM 0x38
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#define REG_OFON 0x39
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#define REG_TSLB 0x3a
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#define REG_COM11 0x3b
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#define REG_COM12 0x3c
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#define REG_COM13 0x3d
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#define REG_COM14 0x3e
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#define REG_EDGE 0x3f
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#define REG_COM15 0x40
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#define REG_COM16 0x41
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#define REG_COM17 0x42
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#define REG_REG4B 0x4b
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#define REG_DNSTH 0x4c
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#define REG_MTX1 0x4f
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#define REG_MTX2 0x50
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#define REG_MTX3 0x51
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#define REG_MTX4 0x52
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#define REG_MTX5 0x53
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#define REG_MTX6 0x54
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#define REG_BRIGHT 0x55
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#define REG_CONTRAS 0x56
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#define REG_CONTRAS_CENTER 0x57
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#define REG_MTXS 0x58
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#define REG_LCC1 0x62
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#define REG_LCC2 0x63
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#define REG_LCC3 0x64
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#define REG_LCC4 0x65
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#define REG_LCC5 0x66
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#define REG_MANU 0x67
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#define REG_MANV 0x68
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#define REG_GFIX 0x69
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#define REG_GGAIN 0x6a
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#define REG_DBLV 0x6b
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#define REG_AWBCTR3 0x6c
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#define REG_AWBCTR2 0x6d
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#define REG_AWBCTR1 0x6e
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#define REG_AWBCTR0 0x6f
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#define REG_SCALING_XSC 0x70
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#define REG_SCALING_YSC 0x71
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#define REG_SCALING_DCWCTR 0x72
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#define REG_SCALING_PCLK_DIV 0x73
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#define REG_REG74 0x74
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#define REG_REG75 0x75
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#define REG_REG76 0x76
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#define REG_REG77 0x77
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#define REG_SLOP 0x7a
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#define REG_GAM1 0x7b
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#define REG_GAM2 0x7c
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#define REG_GAM3 0x7d
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#define REG_GAM4 0x7e
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#define REG_GAM5 0x7f
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#define REG_GAM6 0x80
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#define REG_GAM7 0x81
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#define REG_GAM8 0x82
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#define REG_GAM9 0x83
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#define REG_GAM10 0x84
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#define REG_GAM11 0x85
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#define REG_GAM12 0x86
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#define REG_GAM13 0x87
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#define REG_GAM14 0x88
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#define REG_GAM15 0x89
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#define REG_RGB444 0x8c
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#define REG_DM_LNL 0x92
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#define REG_DM_LNH 0x93
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#define REG_LCC6 0x94
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#define REG_LCC7 0x95
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#define REG_BD50ST 0x9d
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#define REG_BD60ST 0x9e
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#define REG_HAECC1 0x9f
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#define REG_HAECC2 0xa0
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#define REG_SCALING_PCLK_DELAY 0xa2
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#define REG_NT_CTRL 0xa4
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#define REG_AECGMAX 0xa5
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#define REG_LPH 0xa6
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#define REG_UPL 0xa7
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#define REG_TPL 0xa8
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#define REG_TPH 0xa9
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#define REG_NALG 0xaa
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#define REG_BD60MAX 0xab
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#define REG_STR_OPT 0xac
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#define REG_STR_R 0xad
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#define REG_STR_G 0xae
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#define REG_STR_B 0xaf
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#define REG_ABLC1 0xb1
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#define REG_THL_ST 0xb3
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#define REG_THL_DLT 0xb5
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#define REG_AD_CHB 0xbe
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#define REG_AD_CHR 0xbf
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#define REG_AD_CHGb 0xc0
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#define REG_AD_CHGr 0xc1
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#define REG_SATCR 0xc9
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#define I2C_ADDRESS 0x42
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uint8_t ImageBuffer[CAMERA_IMAGE_WIDTH * CAMERA_IMAGE_HEIGHT / 8];
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static volatile int CurrentLine = 0;
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uint8_t LineBuffer[CAMERA_IMAGE_WIDTH + 40];
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int LineCount = 0;
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static volatile int FrameCount = 0;
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volatile int Camera_Captured = 0;
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static unsigned int BlackPixels = 0;
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#ifdef CONFIG_USE_EXPOSURE_CORRECTION
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static volatile int ExposureCorrection = 0;
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#endif
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volatile unsigned int Camera_BlackPixelCounts[] = {0};
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volatile int Camera_FinalFrameCount = -1;
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static uint8_t ReadRegister(uint8_t reg)
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{
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while(I2C1->SR2 & I2C_SR2_BUSY);
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I2C1->CR1 |= I2C_CR1_START;
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while(~I2C1->SR1 & I2C_SR1_SB);
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I2C1->DR = I2C_ADDRESS;
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while(~I2C1->SR1 & I2C_SR1_ADDR);
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I2C1->SR2; // Dummy read
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I2C1->DR = reg; // Write the register number to be read
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while(~I2C1->SR1 & (I2C_SR1_TXE | I2C_SR1_BTF));
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I2C1->CR1 |= I2C_CR1_STOP;
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// Read the register value
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while(I2C1->SR2 & I2C_SR2_BUSY);
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I2C1->CR1 |= I2C_CR1_START;
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while(~I2C1->SR1 & I2C_SR1_SB);
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I2C1->DR = I2C_ADDRESS | 1;
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while(~I2C1->SR1 & I2C_SR1_ADDR);
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I2C1->SR2; // Dummy read
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I2C1->CR1 |= I2C_CR1_STOP;
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while(~I2C1->SR1 & I2C_SR1_RXNE);
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uint8_t data = I2C1->DR;
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return data;
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}
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static void WriteRegister(uint8_t reg, uint8_t value)
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{
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while(I2C1->SR2 & I2C_SR2_BUSY);
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I2C1->CR1 |= I2C_CR1_START;
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while(~I2C1->SR1 & I2C_SR1_SB);
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I2C1->DR = I2C_ADDRESS;
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while(~I2C1->SR1 & I2C_SR1_ADDR);
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I2C1->SR2; // Dummy read
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I2C1->DR = reg; // Write the register number
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while(~I2C1->SR1 & (I2C_SR1_TXE | I2C_SR1_BTF));
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I2C1->DR = value; // Write the register value
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while(~I2C1->SR1 & (I2C_SR1_TXE | I2C_SR1_BTF));
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I2C1->CR1 |= I2C_CR1_STOP;
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}
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void Camera_Init(void)
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{
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
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RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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// Reset pin
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GPIOB->CRH = (GPIOB->CRH
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& ~(0x0f << (4 * PIN_CAMERA_RESET - 32)))
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| (0x01 << (4 * PIN_CAMERA_RESET - 32)) // Output, max. 10 MHz
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;
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GPIOB->BRR = (1 << PIN_CAMERA_RESET);
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GPIOB->BSRR = (1 << PIN_CAMERA_RESET);
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// Enable MCO for camera main clock line (PLL / 2 -> 24 MHz)
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RCC->CFGR |= RCC_CFGR_MCO;
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GPIOA->CRH = (GPIOA->CRH
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& ~(0x0f << (4 * PIN_CAMERA_MCLK - 32)))
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| (0x0b << (4 * PIN_CAMERA_MCLK - 32)) // Output, max. 50 MHz
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;
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AFIO->MAPR |= AFIO_MAPR_I2C1_REMAP;
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// I2C interface for camera configuration
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GPIOB->CRH = (GPIOB->CRH
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& ~(0x0f << (4 * PIN_CAMERA_SCL - 32))
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& ~(0x0f << (4 * PIN_CAMERA_SDA - 32)))
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| (0x0e << (4 * PIN_CAMERA_SCL - 32)) // AF OD output, 2 MHz
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| (0x0e << (4 * PIN_CAMERA_SDA - 32)) // AF OD output, 2 MHz
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;
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I2C1->CR1 = I2C_CR1_SWRST;
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I2C1->CR1 = 0;
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I2C1->CR2 = (24 << I2C_CR2_FREQ_Pos);
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I2C1->CCR = I2C_CCR_FS | I2C_CCR_DUTY | (1 << I2C_CCR_CCR_Pos) | 5;
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I2C1->CR1 = I2C_CR1_PE;
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// Timer setup
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AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_PARTIALREMAP;
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GPIOB->CRL = (GPIOB->CRL
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& ~(0x0f << (PIN_CAMERA_HSYNC * 4))
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& ~(0x0f << (PIN_CAMERA_PCLK * 4)))
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| (0x04 << (PIN_CAMERA_HSYNC * 4)) // Floating input
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| (0x04 << (PIN_CAMERA_PCLK * 4)) // Floating input
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;
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GPIOA->CRH = (GPIOA->CRH
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& ~(0x0f << (PIN_CAMERA_VSYNC * 4 - 32)))
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| (0x04 << (PIN_CAMERA_VSYNC * 4 - 32)) // Floating input
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;
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// TIM1_CH2 is VSYNC
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TIM1->PSC = 0;
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TIM1->ARR = 65535;
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TIM1->CCMR1 = TIM_CCMR1_CC2S_0;
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TIM1->CCER = TIM_CCER_CC2E;
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TIM1->DIER = TIM_DIER_CC2IE;
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NVIC_SetPriority(TIM1_CC_IRQn, 0);
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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// TIM3_CH2 is HSYNC and should trigger an interrupt, while TIM3_CH1 is the
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// pixel clock and should trigger DMA transfers
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TIM3->PSC = 0;
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TIM3->ARR = 1;
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TIM3->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1PSC_1;
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TIM3->CCER = TIM_CCER_CC2P | TIM_CCER_CC2E | TIM_CCER_CC1E | TIM_CCER_CC1P;
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TIM3->DIER = TIM_DIER_CC2IE;
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NVIC_SetPriority(TIM3_IRQn, 0);
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NVIC_EnableIRQ(TIM3_IRQn);
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// Fetch GPIOA IDR lower byte
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DMA1_Channel6->CPAR = (uint32_t)&(GPIOA->IDR);
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// Startup delay
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for(volatile int i = 0; i < 1000; i++);
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// Camera configuration
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ReadRegister(REG_PID);
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// Disable timing resets
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WriteRegister(REG_COM6, 0x00);
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// Set clock prescaler to 2
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WriteRegister(REG_CLKRC, 0x4 | 1);
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// Enable scaling
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WriteRegister(REG_COM3, 0x08);
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// Use QCIF output format
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WriteRegister(REG_COM7, 0x08);
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// Blank pixel clock during sync pulses
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WriteRegister(REG_COM10, 0x20);
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// Enable pixel clock scaling
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WriteRegister(REG_COM14, 0x18 | 1);
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WriteRegister(REG_SCALING_PCLK_DIV, 1);
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// Set maximum gain ceiling
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WriteRegister(REG_COM9, 0xca);
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// Disable auto-exposure, enable auto-gain
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WriteRegister(REG_COM8, 0xec);
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// // Disable auto-gain, enable auto-exposure
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// WriteRegister(REG_COM8, 0xe9);
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// Use histogram-based auto-exposure
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WriteRegister(REG_NALG, 0x94);
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// Increase AEC speed:
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// ‘Decrease TPL but not less than UPL [default 0xc1] and increase TPH but
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// not bigger than LPH [default 0xf0]’
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WriteRegister(REG_TPL, 0xc1);
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WriteRegister(REG_TPH, 0xf0);
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// Enable VSYNC interrupts. TIM3 is enabled at the first VSYNC.
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FrameCount = 0;
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Camera_Captured = 0;
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TIM1->CR1 = TIM_CR1_CEN;
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}
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void TIM1_CC_IRQHandler(void)
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{
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// VSYNC
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if(~TIM3->CR1 & TIM_CR1_CEN)
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{
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// Enable HSYNC interrupts and pixel-clock-initiated DMA transfers
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TIM3->CR1 = TIM_CR1_CEN;
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// Return early
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// Dummy read
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TIM1->CCR2;
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TIM1->SR &= ~TIM_SR_CC2IF;
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return;
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}
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LineCount = CurrentLine;
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CurrentLine = 0;
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FrameCount++;
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#ifdef CONFIG_USE_EXPOSURE_CORRECTION
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// Correct exposure across frames
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ExposureCorrection += 32 * BlackPixels / CAMERA_PIXELS - 16;
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#endif
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// Check if the last frame's exposure is reasonable
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if(!Camera_Captured && FrameCount >= CONFIG_MIN_FRAMES
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&& (
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(BlackPixels > (int)(CAMERA_PIXELS / 2
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- CAMERA_PIXELS * CONFIG_TOLERANCE)
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&& BlackPixels < (int)(CAMERA_PIXELS / 2
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+ CAMERA_PIXELS * CONFIG_TOLERANCE))
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|| FrameCount >= CONFIG_MAX_FRAMES
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))
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{
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Camera_Captured = 1;
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Camera_FinalFrameCount = FrameCount;
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// Disable everything
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TIM3->CR1 = 0;
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TIM1->CR1 = 0;
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}
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if(FrameCount < (int)(sizeof(Camera_BlackPixelCounts)
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/ sizeof(Camera_BlackPixelCounts[0])))
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{
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Camera_BlackPixelCounts[FrameCount] = BlackPixels;
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}
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// Reset black pixel counter
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BlackPixels = 0;
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// Dummy read
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TIM1->CCR2;
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TIM1->SR &= ~TIM_SR_CC2IF;
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}
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void TIM3_IRQHandler(void)
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{
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// HSYNC
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TIM3->DIER &= ~TIM_DIER_CC1DE;
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TIM3->SR &= ~TIM_SR_CC1IF;
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DMA1_Channel6->CCR = 0;
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DMA1_Channel6->CNDTR = sizeof(LineBuffer);
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DMA1_Channel6->CMAR = (uint32_t)LineBuffer;
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DMA1_Channel6->CCR = DMA_CCR_PL | DMA_CCR_MINC | DMA_CCR_EN;
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TIM3->DIER |= TIM_DIER_CC1DE;
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#ifdef CONFIG_USE_2D_DITHERING
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static int8_t y_errors[CAMERA_IMAGE_WIDTH + 2] = {0};
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if(CurrentLine == 0)
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{
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memset(y_errors, 0, sizeof(y_errors));
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}
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#endif
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if(!Camera_Captured && (~CurrentLine & 1)
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&& (CurrentLine / 2 < CAMERA_IMAGE_HEIGHT))
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{
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#ifdef CONFIG_USE_2D_DITHERING
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// Apply errors propagated from the previous line. Since y_errors is
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// overwritten during x error diffusion, this is done now.
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for(int i = 0; i < CAMERA_IMAGE_WIDTH; i++)
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{
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LineBuffer[i + 15] += y_errors[i + 1];
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y_errors[i + 1] = 0;
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}
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#endif
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int x_error = 0;
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for(int i = 0; i < CAMERA_IMAGE_WIDTH; i++)
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{
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int pixel = LineBuffer[i + 15] + x_error;
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#ifdef CONFIG_USE_EXPOSURE_CORRECTION
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if(ExposureCorrection < 0)
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{
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if(pixel < -ExposureCorrection)
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pixel = 0;
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else
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pixel += ExposureCorrection;
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}
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else
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{
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if(pixel > 255 - ExposureCorrection)
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pixel = 255;
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else
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pixel += ExposureCorrection;
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}
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#endif
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int line = CurrentLine / 2;
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int error;
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if(pixel < 127)
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{
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error = pixel;
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ImageBuffer[(line * CAMERA_IMAGE_WIDTH + i) / 8] |=
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0x80 >> (i % 8);
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BlackPixels++;
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}
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else
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{
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error = pixel - 255;
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ImageBuffer[(line * CAMERA_IMAGE_WIDTH + i) / 8] &=
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~(0x80 >> (i % 8));
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}
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#ifdef CONFIG_USE_2D_DITHERING
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// Error propagated to the next pixel in the same line
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x_error = error * 7 / 16;
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||
|
||
// Error distributed to the next line's pixels (offset by 1 so
|
||
// bounds checking isn't necessary)
|
||
y_errors[i] += error * 3 / 16;
|
||
y_errors[i + 1] += error * 5 / 16;
|
||
y_errors[i + 2] = error * 1 / 16;
|
||
#else
|
||
x_error = error;
|
||
#endif
|
||
}
|
||
}
|
||
|
||
CurrentLine++;
|
||
|
||
// Dummy read
|
||
TIM3->CCR2;
|
||
TIM3->SR &= ~TIM_SR_CC2IF;
|
||
}
|