From eaba889f81c973c793be25f645f96470eaa34dd8 Mon Sep 17 00:00:00 2001 From: fruchti Date: Sat, 18 Jul 2020 17:23:10 +0200 Subject: [PATCH] Enable image capture after camera initialisation --- build-number.txt | 2 +- src/ov7670.c | 21 ++++++++++++++++++--- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/build-number.txt b/build-number.txt index 2e9c1e1..faea12c 100644 --- a/build-number.txt +++ b/build-number.txt @@ -1 +1 @@ -558 +561 diff --git a/src/ov7670.c b/src/ov7670.c index f1593c6..377c613 100644 --- a/src/ov7670.c +++ b/src/ov7670.c @@ -218,7 +218,6 @@ void Camera_Init(void) GPIOB->BRR = (1 << PIN_CAMERA_RESET); GPIOB->BSRR = (1 << PIN_CAMERA_RESET); - // Enable MCO for camera main clock line (PLL / 2 -> 24 MHz) RCC->CFGR |= RCC_CFGR_MCO; GPIOA->CRH = (GPIOA->CRH @@ -261,7 +260,6 @@ void Camera_Init(void) TIM1->CCMR1 = TIM_CCMR1_CC2S_0; TIM1->CCER = TIM_CCER_CC2E; TIM1->DIER = TIM_DIER_CC2IE; - TIM1->CR1 = TIM_CR1_CEN; NVIC_SetPriority(TIM1_CC_IRQn, 0); NVIC_EnableIRQ(TIM1_CC_IRQn); @@ -272,7 +270,6 @@ void Camera_Init(void) TIM3->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1PSC_1; TIM3->CCER = TIM_CCER_CC2P | TIM_CCER_CC2E | TIM_CCER_CC1E | TIM_CCER_CC1P; TIM3->DIER = TIM_DIER_CC2IE; - TIM3->CR1 = TIM_CR1_CEN; NVIC_SetPriority(TIM3_IRQn, 0); NVIC_EnableIRQ(TIM3_IRQn); @@ -303,11 +300,29 @@ void Camera_Init(void) // Enable pixel clock scaling WriteRegister(REG_COM14, 0x18 | 1); WriteRegister(REG_SCALING_PCLK_DIV, 1); + + // Enable VSYNC interrupts. TIM3 is enabled at the first VSYNC. + FrameCount = 0; + Camera_Captured = 0; + TIM1->CR1 = TIM_CR1_CEN; } void TIM1_CC_IRQHandler(void) { // VSYNC + if(~TIM3->CR1 & TIM_CR1_CEN) + { + // Enable HSYNC interrupts and pixel-clock-initiated DMA transfers + TIM3->CR1 = TIM_CR1_CEN; + + // Return early + // Dummy read + TIM1->CCR2; + TIM1->SR &= ~TIM_SR_CC2IF; + return; + } + + LineCount = CurrentLine; CurrentLine = 0; FrameCount++;