A squashed, should only change a few lines and no mucking about with submodules
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4 changed files with 8 additions and 8 deletions
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@ -45,9 +45,8 @@ Extra copyright info:
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//Creates an I2S SR of 93,750 Hz, or 3 MHz Bitclock (.333us/sample)
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// 12000000L/(div*bestbck*2)
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//It is likely you could speed this up a little.
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#define LUXETRON
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#ifdef LUXETRON
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#if LUXETRON == 1
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#define INVERT
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#define WS_I2S_BCK 14
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#define WS_I2S_DIV 5
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