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Make STM32F303x6/x8 vs xB/xC

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This commit is contained in:
CNLohr 2020-08-05 04:41:18 -04:00
parent fdabac3b0d
commit 2146a5c3f5
7 changed files with 179 additions and 24 deletions
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8
embeddedstm32f303/lib/stm32f303.ld
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@ -3,7 +3,7 @@ ENTRY( Reset_Handler )
/* Highest address of the user mode stack .*/
_estack = 0x2000a000; /* end of 40K RAM */
_estack = 0x20003000; /* end of 40K RAM */
/* Generate a link error if heap and s tack dont fit int o RAM */
@ -12,9 +12,9 @@ _Min_Stack_Size = 0x200; /* required amount of stack .*/
MEMORY
{
FLASH ( rx ) : ORIGIN = 0x08000000 , LENGTH = 256K
RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 40K
CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 8K
FLASH ( rx ) : ORIGIN = 0x08000000 , LENGTH = 32K
RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 12K
CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 4K
}
SECTIONS

9
embeddedstm32f303/lib/system_stm32f30x.c
View file

@ -341,8 +341,15 @@ static void SetSysClock(void)
/* PLL configuration */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
//If we're using an 8 MHz crystal.
#ifdef TQFP32
// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); // 8 * 9 = 72 MHz
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL8); //8 * 8 = 64 MHz
#else
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL2); //25MHz*2 = 50 MHz
#endif
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;